Flexible computer accessed telemetry

ABSTRACT

Flexible, computer-accessed telemetry is provided by a sequence control unit, auxiliary memory and system control registers to permit sensors and digital data sources to be sampled in a programmed format with various groups of samples taken at different rates. Each programmed sample may be processed for transmission in a specified way by including an operation code with the programmed address code used to select the designated sensor or digital data source. Index registers and a scratch pad memory permit flexibility in programming sample sequencing formats. A particular format may be started, stopped and altered by ground station commands received through a receiver, or directly by a digital computer.

United States Patent Low et a1.

[54] FLEXIBLE COIVIPUTER ACCESSED TELEMETRY [72] Inventors: George M.Low, Acting Administrator of the National Aeronautics and SpaceAdministration with respect to an invention of; Richard A. Easton, 1760State Street 040, South Pasadena, Calif, 91030; Edward E. Hilbert, 195South Wilson Avenue, Pasadena, Calif. 91 106 [22] Filed: Feb. 19, 197121 Appl. No.: 116,786

[52] US. Cl ..340/l72.5, 179/15 BV [51] Int. Cl. 5/06,H041 7/08 [58]Field ofSearch..... ..340/172.5, 150; 178/50, 69.5;

[56] References Cited UNITED STATES PATENTS 3,380,020 4/1968 Clark..340/l72.5 X

3,421,147 1/1969 Burton etal ..340/172.5

3,497,627 2/1970 Blasbalg et a1 ..l79/l5 BV DIGITAL COMPUTER AUXILIARYMEMORY 451 May 23, 1972 Primary Examiner-Paul J. Henon AssistantExaminer-Jan E. Rhoads Attorney-Monte F. Mott, Paul F. McCalul and JohnR. Manning 1 1 ABSTRACT Flexible, computer-accessed telemetry is pmvidedby a sequence control unit, auxiliary memory and system controlregisters to permit sensors and digital data sources to be sampled in aprogrammed format with various groups of samples taken at differentrates. Each programmed sample may be processed for transmission in aspecified way by including an operation code with the programmed addresscode used to select the designated sensor or digital data source. Indexregisters and a scratch pad memory permit flexibility in programmingsample sequencing formats. A particular format may be started, stoppedand altered by ground station commands received through a receiver, ordirectly by a digital computer.

12 Claims, 6 Drawing Figures TRANS- MITTER OUTPUT DATA BUFFER 8. TRANS-UNIT MISSION CHANNEL DATA U PROCESSING AND DECODER bTcTTAL DATA 1SOURCFS \N GN MONITORING UNIT PATENIEIIIIII23 I972 I 3.665417 saw 1 or 5H GI COMMAND" RF 1 1 DIGI IAI RICEIVER TRANS COMPUTER Q I I3INRUT-OUTPUTF ,15

UNIT IO E 1 L \C M I EI L 'l L T OUTRUT I DATA SEQUENCEII'W AUXILIARY IBUFFER CONTROL MEMORY I & TRANS UNIT UNIT I MISSION SE 1 I 1 t CHANNELSYSTEM CONTROL REGISTERS I 23 I SELECT CONTROL I UNIT I l B1 to B7 1 IREAL I EISEJIT /D I DATA G nu l 20 O BUFFER ANALOG SENSORS l I9 I 81 to87 w T l DECODER DATA t L L PROCESSING SE M AND MONITORING l UN IT IDIGITAL W L 1 DATA 01 S P7 l SOURCE SIT' G :I INVENTORS RICHARD A.EASTON EDWARD E. HiLBE'RT F I G. 1 IA-W PATENTEDIIAI 2 3 I972 SHEET 3 OF5 5 FRAME DLY \I S COUNT REGISTER TRANSFER DELAY DLYI I COUNTER FRAME 46AND RETURN DECODER DECODER START I 1 I L 2 P! O 1 DLY NEW PRESENT )44 aINDEX INDEx S3 63 REGISTER REGISTER DLY 61 53 I' 527 I h CONTROL IMEMORY ADDRESS REGISTER S5 A ADDRESSING (CTLADR/CT) I UNIT I i SELECTIONI MAGNETIC ADDRESS REGISTER CORE (DATAlD/LP) -41 I MEMORY l I---l1---l II J\ .DS

OP CODE ADDRESS CODE BITS TO TO SELECTION UNITS CONTROL UNIT 23 ISSIOAND DECODER 26 INVENTORS EDWARD E. Y

RICHARD A. EASTON HILBERT STEP PATENTE0IIIII23 I972 3.665.417

STAR T TRANSFER CONTENT OF NEW INDEX REG.

TO PRESENT INDEX REG. (INITIAL NO OR CONTENT IS 000) I LOAD CTLADR/CT INCONTROL ADDRESS I REG. FROM MEMORY LOCATION SPECI L OP I FIED BY PRESENTINDEx REG. AND FRAME RETURN FLAG (FRF),i.e.+O or +16 LOAD DELAY COUNTFOR PRESENT RATE IN TR. DELAY COUNTER & IDENT. OF NExT RATE GROUP IN NEWINDEx REG. FROM MEMORY LOCATION SPECI- FIED BY PRESENT INDEx REG.+3,I.e.+8

NO OF.

LOAD EDATAID/LPTHEROM MEMORY LOC. SPECIFIED BY CTLADR IN CONT. REG.

NO DLYIO YES INCR, FRAME COUNT REG. S6

NO OF! 7 NO OP.

NO OP.

F I G. 6

INVENTORS RICHARD A. EASTON BY EDWARD E. HILBERT STOP FLEXIBLE COMPUTERACCESSED 'I'ELEMETRY ORIGIN OF INVENTION The invention described hereinwas made in the performance of work under a NASA contract and is subjectto the provisions of Section 305 of the National Aeronautics and SpaceAct of 1958, Public Law 85,568 (72 Stat. 435; 42 USC 2457).

BACKGROUND OF THE INVENTION This invention relates to data telemetry andmore particularly to programmed telemetry which can be accessed by acomputer to change the program for greater flexibility.

In the past data telemetry systems have been provided with asubstantially fixed sampling sequence derived from a clock controlledcommutator. In the extreme, the commutator has been comprised ofstepping switches with one or more decks for sampling different groupsof sensors or digital data sources at different rates. To change thesequence, a physical change was required in the clocks. In more recentsystems using solid state commutators, the task of changing the sequencerequired changes in logic or selection networks. It would be desirableto provide a flexible telemetry system which can be readily changed by acomputer under control of a stored program or by external commands. Sucha system would have great advantage in many applications, particularlyspace exploration applications where changing conditions requiredifferent sequencing formats at different stages of the explorationmission, particularly for outer planet missions which will last anywherefrom eight to twelve years.

SUMMARY OF THE INVENTION In accordance with the present invention, acomputer-accessed telemetry system is provided to control sampling ofanalog and digital data from a plurality of sources, each data sourcebeing identified by a unique code. The system comprises an auxiliarymemory unit which stores the identification codes of sources to besampled in groups according to the rate at which they are to be sampled,each group being stored in sequential locations of a separate block ofmemory. Three additional blocks of memory are reserved for sequencecontrol, each block having a number of memory locations for acorresponding number N of distinct rates of R, R12, R/Z, ...,R/2", whereR is the maximum rate at which any source may be sampled for a givensequencing format, and N is equal to n+1. One block of N locations isused to store a control word for each rate which specifies the memorylocation of the first source identification code to be sampled in theparticular rate. Each time the control word is used to obtain a sourceidentification code, a sequence control unit increments the control wordand stores it in a memory location of another block (scratch pad) of Nlocations associated with the first by the rate of the group controlledby the word. The control word or each group includes a flag bit (CT) setequal to l for only the last group to be serviced in order. The thirdblock of N memory locations is reserved for storing the number ofsamples to be included in each group. That provides controlled delay forthe sequence control unit between groups. The control unit automaticallycycles through programmed groups, taking the number of samples of eachgroup in sequence (as specified by the number stored in an associatedmemory location of the third block of N locations) before storing thecontrol word associated therewith in the associated scratch padlocation. The control unit then obtains a new control word for the nextgroup from the memory location associated with that next rate group.

The delay control number for the previous rate group, as read from alocation in the third block of N locations, includes a field of binarydigits uniquely identifying both the rate and the associated memorylocation in the first, second and third blocks of memory. That field isstored in a first register while the previous rate group is beingserviced and then transferred to a second register for use whileservicing the identified rate group. Once a control word has been read,incremented and stored in the associated scratch pad memory location, itis retrieved from scratch pad memory for subsequent servicing of therate group. A counter counts the CI flags included with the controlwords (which flags are also stored in scratch pad memory as part of thecontrol words) to permit a determination of when the sequence controlunit should go back to the first block of N memory locations to obtainthe original control word for a given rate group, thus recycling withinthe rate group automatically. Each data source identification read fromthe auxiliary memory includes a flag LP which, when programmed as a bit1, will inhibit the control word (for the group in which included) frombeing incremented, thus providing for multiple sampling in rapidsuccession. A computer may alter the program at any time by stopping thesequencing unit after any seven-step cycle in progress and altering thesequencing format in memory before starting the sequencing unit again.

The novel features that are considered characteristic of this inventionare set forth with particularity in the appended claims. The inventionwill best be understood from the following description when read inconjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of aprogrammable telemetry system according to the present invention.

FIG. 2 is a timing diagram for a sequence control unit of the system ofFIG. I.

FIG. 3 is a schematic diagram of a timing circuit for producing thetiming signals of FIG. 2.

FIG. 4 is a schematic diagram of the sequence control unit of FIG. 1 forcontrol of processing a programmed sequencing format stored in anauxiliary memory unit through control registers in accordance with apreferred embodiment of the present invention.

FIG. 5 is an examplary sample sequencing format to be processed inaccordance with the present invention.

FIG. 6 is a flow chart for operation of the apparatus of FIG. 4.

DESCRIPTION OF PREFERRED EMBODIMENTS FIG. I shows the generalorganization of a programmable access telemetry system 10 in aspacecraft having a general purpose (GP) digital computer 11 and acommand receiver 12. An input-output (I/O) unit 13 is provided to enablethe GP computer to receive commands from a ground station through thereceiver 12 and to cause the system 10 to transmit spacecraft data,either on a real-time basis directly through a transmitter 14 or on aprogrammed basis through an output data buffer and transmission channell5.

It should be noted that while a programmable access telemetry system hasbeen shown in a spacecraft application, the present invention embodiedtherein is not limited to spacecraft applications. As notedherein-before, the present invention departs from the prior arttechnique of sampling data in a fixed sequence set by a clock-controlledcommutator to sampling data in a sequence set by a program stored in anauxiliary memory unit I6 of the telemetry system. The memory unit ispreferably a random access memory shared by the GP computer via the [/0unit 13 and a telemetry sequence control unit 17. Accordingly, thetelemetry system and the command receiver are both essentially simplyexternal or peripheral units coupled to the GP computer 11 in aconventional manner through the I/O unit.

I/O units for scientific applications are often designed for theparticular application, as are the GP computers, particularly inspacecraft applications because of size, weight and power restrictions.However, standard or commercial computers and [/0 units designed forscientific applications may be employed in other applications, such asmarinecraf't applications. For example, the SDS-930 computer with a datamultiplexing system supplementing the standard l/O unit of the computercould be used, but the SDS-920 computer with standard input outputbuffers would be adequate for those applications which do not have highdata rates. In most applications, the GP computer will interface withstill other systems not shown.

The sequence control unit is started by a START command signal from theGP computer to initiate a programmed data sampling sequence stored inthe memory unit as index words" and control wor which can be altered bythe GP computer, to change the rate at which certain data is sampled,for example. The sampling sequence programmed is repeated until thedigital computer stops the sequence control unit with an EXIT command.The ground station can also start, stop and alter the sampling sequencethrough commands entered into the computer via the command receiver 12and I/O unit 13. For more direct ground control, the 1/0 unit can beprovided with direct communication channels from the receiver to thesequence control unit and memory unit. However, for simplicity it isassumed that communication is through the GP computer in this exemplaryembodiment.

Basically, the sequence control unit functions as a special purposecontrol computer using a nested DO loop procedure, i.e., using iterativesubroutines to sample data at any desired frequency. Every sampleordered is called for by a stored program. Because that program can bearbitrarily altered at will, sampling can be said to be with randomaccess. However, in order not to tie up the GP computer and/or thecommand receiver, the system operates independently and the programmedsequence is changed by the GP computer 11 only as circumstances require,such as when data from a given sensor exceeds limits so as to requiremore frequent sampling of that sensor while remedial action is beingtaken, or when a command is received from a ground control stationthrough the receiver 12.

This programming flexibility also makes it possible to sample andgenerate two or more simultaneous sequences at once so that one can betransmitted to ground in real time, while a different one is beingprocessed, monitored and/or stored for later transmission via thechannel 15. The data processing is selected for each particular datasource and may include data and data compression according to any one ofa plurality of known techniques. The latter may be used to alert the GPcomputer of a condition which requires more frequent sampling, remedialaction or some other action under supervisory control of the GPcomputer. The real time data transmission is accomplished through a databuffer 18 which allows data samples at random times to be stored fortransmission at regular times and may also allow for data compressionusing any one of a plurality of known techniques selected for theparticular samples. Such a technique for buffering real time data isstandard. The data processing and monitoring techniques contemplated forinclusion in unit 19 are also standard. What is new is provision for areadily alterable program with either real time data sampling andtransmission, or data processing and monitoring of sampled data withdelayed transmission of some or all data, or both simultaneously. Thesequence control unit to be described more fully with reference to FIG.4 makes this flexibility possible.

The data being sampled enamates from either analog sensors representedby a block 20 or other data sources such as scientific instruments whichprovide data already in digital form. The digital data sources arerepresented by a block 21. In either case, there are the two possiblemajor paths for data in the system, one for real time data transmissionvia the buffer 18, and one for data processing and monitoring withpossible delayed transmission) via the unit 19.

The outputs of the analog sensors are applied to a selecting circuit 22,such as a selecting tree. A control unit 23 receives address codes froma unit of system control registers 24 to select a sensor for samplingand analog-to-digital conversion in an A/D converter 25 under timingcontrol of the sequence control unit 17. The system control registersare loaded from memory under timing control of the unit 17. A digitaldata source is similarly selected through a decoder 26 which enables aselected one of AND gates G, to G,, associated with the desired datasource. When one of the gates G to G, is not being selected, the gate G,is thus selecting the AID converter as the data source. That is readilyaccomplished by reserving for the analog sensors the lower half of the2" selecting codes possible with an n-bit code. The gate G, is thenenabled only when the most significant bit is false, and one of thegates G to G, is enabled when the most significant bit is true. An ORgate 27 couples the outputs of the AND gates G, to G, to the data buffer18 and the data processing and monitoring unit 19. The selection of adata source is controlled by a field of binary digits in the selectionbeing stored in one of the system control registers for the givensample.

The A/D converter is provided with an output register, such as aseven-bit register, in which the digital value of the analog signal isdeveloped. For example, using the successive-approximations technique,the bits are set true in the register in sequence starting with the mostsignificant bit position, and the output of the register is convertedback into analog form for comparison with the sample stored in asample-and-hold circuit. if the sample signal is exceeded, the last bitset is reset, and the process of conversion continues until all sevenbits have been properly set in just eight clock periods. The clockperiods are metered by clock pulses (CP) from a high frequencyoscillator 30 shown in FIG. 3. Once eight clock pulses have beenapplied, following a sample pulse from the sequence control unit 17,further application of CP pulses to the output register is inhibiteduntil the next sample pulse occurs. In the meantime seven shift controlpulses B to B are applied to the output register for serial readoutthrough the gate G Data from selected digital data sources are similarlyread from output registers in the block 21 under control of the shiftcontrol pulses B to B, from the sequence control unit 17.

FIG. 2 shows a timing diagram for these shift control pulses B to B,from the sequence control unit. The selection of sensor, or data source,is made during STEP 5 of the sequence control unit by a select enablesignal (SE). The conversion is then enabled by an A/D signal which istrue for eight clock pulses. The leading edge of the next A/D pulse canbe used to reset the output register for the next conversion cycle, butin practice that register is simply cleared as the seven-bit number isshifted out. For a digital data source, the signal SE is used to readinto buffer registers within the block 21 data from all of the sources.The seven shift pulses B to B, are then used to simultaneously read outthe data words in series. The decoder 26 then selects only one dataword. This organization is feasible because the bank of buffer registersnecessary can be readily provided using integrated circuit technology.An alternative organization would be to provide only one buffer registerand banks of selection gates to read out only one digital data source inparallel into that register in response to the signal SE. The shiftpulses would then be employed to serially transfer the data word to thedata buffer 18 and monitoring unit 19. These arrangements are suggestedby way of example, and not limitation; still other equivalentarrangements within the scope of the invention will occur to thoseskilled in the art.

The sequence control unit includes a sequencing section shown in FIG. 3for producing the timing signals shown in H0. 2. System clock pulsesfrom a source 30 are counted by a counter 31 (to divide the clock pulsesby 32, for example). The lower rate pulses are then applied to atwo-phase clock generator 32, thereby producing phase displaced clockpulses (l and 0 at the lower rate. A START command signal from the GPcomputer sets a flip-flop 33 to enable a seven-stage ring counter 34 tobe reset to an initial condition (state 1) in response to a pulsegenerated by a difi'erentiating network, 35 and to enable the ringcounter to be operated by 0 clock pulses via a gate 36. As successivestages of the counter are turned on in sequence, signals from the stagesmark the seven steps of a sample sequencing cycle. Each step signalgates a 0, pulse through one of a bank of gates 37 to produce a sequenceof pulses, S to 5-,.

All of the signals S to S-, are combined through an OR gate 38 toproduce a continuous train of shift pulses (B, to B The STEP 5 signal,from which the pulse S, is derived, is employed as the select enablesignal SE referred to hereinbefore. [t is also employed to enable adecoder 39 connected to the counter 31 to set a flip-flop 40 at apredetermined count (for example 18) and to reset the flip-flop eightsystem clock pulses later. The output of the flip-flop is then employedas a control signal AIDE to enable the A/D converter 25. A sensor isthus selected, and a sample taken, during the first l8 periods of thesystem clock pulses. Conversion then takes place during the next 8periods of the system clock pulses. Thereafter, bit pulses B, to 8-,read out the digital number.

If an analog sensor is not selected, the gate G, is not enabled, thuseffectively shutting out the A/D converter. ln practice, operation ofthe A/D converter would be inhibited when an analog sensor is not beingselected to avoid unduly exercising the A/D converter.

The control lines and serial data transmission lines in the system thusfar described are properly represented as single lines, except theselection lines from system control registers 24 to the sensor selectcontrol unit 23 and decoder 26; those lines are represented by heavylines to be cables because they include separate lines for paralleltransmission of a selection code, such as an eight-bit code for a systemof 511 possible analog sensors and digital data sources to be selected.As each sensor or data source is selected in response to a selectioncode read from memory, the channel and mode of channel operation areselected by an operation code taken from a different field of the sameword read from memory to obtain the selection code. Accordingly, cablesare shown for parallel transfer of words to and from the system controlregisters, and to the buffer 18 and data processing unit 19. Cables arealso shown for parallel transfer of data words to the memory unit forstage and/or transfer to the GP computer via the unit 13 and from the GPcomputer to the memory unit via the same unit. In addition, cables areshown between the sequence control unit 17 and both the system controlregisters and the sequence control unit for transmission of the variouscontrol signals.

The sequence control unit 17 includes the timing networks of FIG. 3 andother control logic while the system control registers 24 include as aunit all registers and counters. Since the control unit and controlregisters interact extensively, both will be described in greater detailwith reference to FIG. 4. To further facilitate understanding anexemplary embodiment of the present invention, the auxiliary memory unit16 is shown in FIG. 4 divided into a magnetic core memory 160 and anaddressing unit 16b which controls both storing and reading operationsin a conventional random access core memory system. Thus it should beunderstood that with reference to the organization illustrated in FIG.1, the memory unit 16 and the registers and counters of FIG. 4 are not apart of the sequence control unit; this division is arbitrary and forpurposes of description only.

The memory access rate is l .5 MHz, and can be used to program thesampling of data from one group of up to 256 locations or channels ofsensors and digital data sources (normally 32) at a given rate R; andadditional groups of locations at lower rates R/2, R/4,...,R/2", where nis arbitrarily selected to be equal to seven for a total of eightdifferent rate groups. If 256 is the total number of locations orchannels to be selected, their addressed may be arranged in one ofvarious different rate-group patterns (referred to hereinafter asformats) in memory. The number of different formats possible isvirtually without limit since the total number of different accessiblechannels can be arranged in different combinations and permutations. Foran exemplary implementation, assume the memory locations are allocated(in octal code) for this telemetry system as follows:

USE

LOCATION CONTENT 000-007 CTLADR/CT Scratch pad memory for control words010-017 DELAY/NI Number of samples in prelent group and group rateidentification for next group 020-027 CT LADR CT Control word memory030-377 DATAlD/LP Data source identification memory for next group Eachof the locations reserved for the group rate identification include afield DELAY of six bits to specify the number of data (analog ordigital) sources to be sampled in a given rate group, and a field Nl ofthree bits to specify the least significant octal digit of a memorylocation from 010 to 017 for the next rate group. For example, if it isto be a rate group R/8, the field Nl will store an octal 3, therebyspecifying memory location 013 for the next rate group identification.Assuming the present rate group is 26 at the rate R, the DELAY fieldwill store a number equal to 63-26. As each data source of the presentrate group is sampled, that number is incremented so that when the countof 63 is reached, a signal DLY is generated to advance the programmedsequence control unit to the next rate group specified in memorylocation 013.

The DELAY field for all rate groups of a given format except the firstgroup at rate R, will always be 63-1, so that only one source is sampledbefore another signal DLY again advances the sequence control unit. Forthe rate group R/8, one source is sampled every minor frame (a minorframe being a sequence which runs through all programmed rate groups onetime), and for the first seven minor frames, the location in memory forthe data source identification to be used in the next minor frame isstored in the scratch pad memory at location 003. Thus the octal number3 is used to not only point to a memory location 013 to go from the lastrate group to the present, but also to point to the memory location 003as the place to store a control word address (CTLDR/CT) after it hasbeen incremented in order to fetch the data source identification(DATAlD/LP) for the next source to be samples in that rate group R/8during the next minor frame.

Upon entering a new frame group, such as the rate group R/8 for thefirst time, and every eighth time thereafter, the required control wordaddress (CT LDR/CT) is taken from a location in the sequence 020 to 027associated with that rate group by the least significant octal digit, inthis case location 023. Thereafter, for the intervening minor frames,the control word address is taken from the scratch pad memory locationassociated with that rate group, in this case location 003.

Each control word address carries a flag bit CT which is a binary 0 inall cases for all rate groups, except the last rate group, and a binary1 for the last rate group. Assuming the last rate group is a group of 64data sources or channels as shown in an exemplary format in FIG. 5, fora group rate of R164, the control word address Cl'LADR/CT of the memorylocation (in the block from 030 to 377) selected for the data sourceidentification of the first channel 40 is read from memory location 026,used to select the channel 40, incremented and stored in scratchpadmemory location 006. For example, the CTLADR field may specify memorylocation 126 where the code 040 is to be found. Before being stored inscratch-pad memory, it is incremented to 127 so that during the nextminor frame, the code 041 may be read from memory location 127.

It should be noted that the source identification codes need not begrouped in sequential order since the source selection system describedwith reference to FIG. 1 permits random selection. The next channelcould just as well have been 3l9, or any other of 511 channels. Thelimit of 511 is due to only eight bits being available in the datasource identification (DATAlD/LP) to be read from memory. It should alsobe noted that in this exemplary embodiment, the memory is assumed toinclude only 232 memory locations from 030 to 377 in octal code.Therefore, all 511 channels cannot be included in a programmedsequencing format because one memory location is required to store eachdata source identification code of each included. In other words,although an eight-bit code permits 256 possible source identifications,only 232 can actually be accommodated. If more must be accommodated itwould be a simple matter of providing for more bits in the sourceidentification bit.

One bit of the data source identification word is a flag which isnormally programmed as a binary if the channel specified is to beaddressed only once during the current minor frame. If a channel is tobe sampled a number of times during the minor cycle, the flag LP is setequal to I. That is used to inhibit incrementing the control word(CTLADR/CI), thereby causing the same channel to be addressed until theDELAY number has been incremented to 63. This special feature is useful,for example, to make several readings in rapid succession for thepurpose of computing an average reading without repeating the dataidentification word DATAID in memory at successive memory locations. Inan exemplary format, it is only used for that purpose at the end of thefirst rate group. If it is used in any other rate group, the delaycounter is stored with the number controlling the number of samples tobe taken before entering a new number in the new index register.Thereafter an FRF signal will cause the next control word to be takenfrom the associated memory location in the block from 020 to 027 insteadof from the associated scratch pad memory location in the block 000 to007.

Each source identification word (DATAID/LP) is, as just noted, anine-bit word if only programmed sequencing is to be provided inaccordance with the present invention. In some applications, it isdesirable to program specific data processing for each sample, such asfor real-time data transmissions with a particular type of datacompression or delayed data transmission with data processing andmonitoring. The data processing may, for example, include comparisonwith the last sample to determine whether the change has exceeded apredetermined value. If so, the GP computer may be alerted (over a linenot shown) or the ground station may be alerted by including with thedata to be transmitted a predetermined code. Following that the newsample value will replace the old sample value in the memory with thesource identification, i.e. as a field of the DATAlD/LP word. Toaccomplish that, the DA'I'AID/LP word must include an additional fieldfor an operations code which will specify the data processing to becarried out by the buffer 18 and the data processing and monitoring unit19. How the operations are carried out is not part of this inventionwhich relates to a programmable telemetry system.

Another feature of the system illustrated in FIG. 1 is that the outputdata buffer and transmission channel may be monitored to determine whenthe buffer is getting too full. When that occurs, the unit 19 willreceive a buffer-full signal, and generate a code or interrupt signalwhich will cause the GP computer to alter the sample sequencing formatto a form that will alleviate the buffer-fullness problem. Anotherpossibility would be for the output data buffer to transmitbuffer-fullness data and for the unit 19 to carry out all of themonitoring tasks on bufier fullness. In either case, the importantfeature of the present invention, namely a programmable sequencingformat can be used to advantage in preventing the loss of data due tooverflow of the output data buffer.

This novel arrangement allows sampling rates to be optimizedindividually for each sensor. By changing the program stored in thememory, any sensor or digital data source can be added, deleted, or haveits sampling rate changed without significant change in the sample ratesof others. In addition, disposition of the data can be tailored andchanged at will for each sensor or digital data source.

Before describing the exemplary format shown in FIG. 5 in greaterdetail, the organization and operation of the sequence control unit 17and system control registers will be more fully described with referenceto FIG. 4, and a flow chart shown in FIG. 6. For convenience all of thesystem control reg'sters, namely two index registers, and two addressregisters are shown with the components of the sequence control unit asone integral unit. In addition, the memory unit 16 is reproduced in FIG.4 to facilitate understanding the operation of the sequence controlunit. As noted hereinbefore, the division into functional blocks in FIG.1 is arbitrary, and for purposes of description only.

From the foregoing it will be appreciated that a programmed sequencingformat entails a number of minor frames making up a major frame. Whenthe last of a group sampled at the lowest rate has been completed, themajor frame is complete, and the next minor frame starts a new majorframe. A START command signal initiates the first minor frame of a majorframe, and the major frame is completed again and again, until an EXITcommand resets the flip-flop 33 (FIG. 3).

The step signal generator shown in FIG. 3 cycles once for each sample ordigital data source selected. The selection is made by an addressregister 41 which receives data identification word (DATAID/LP). Thelocation in memory from which this register is loaded is determined bythe control word (CI'LADR/CT) in a control address register 42. Fouradditional registers are required to complete sequence control of minorand major frames. A frame count register 43 is provided to keep track ofwhich minor frame is in progress, and a threebit present index register44 is provided to point to the location in memory from which the controladdress register will be loaded with a control word that determines thememory location from which the address register 41 is loaded for thenext selection. A threebit new index register 45 points to the memorylocation for the next control word to make the next selection aftertaking the allotted number of samples at the present rate, i.e. toprovide transition in the minor frame between sequences at difi erentrates. A transfer delay counter and decoder 46 is also provided in themanner to be described next.

There will be a number (1 to 63) of samples programmed for each rate.For the maximum rate R, the complement of that number is loaded into thetransfer delay counter and decoder 46 from the memory location 010uniquely associated with the rate R. The function of the transfer delaycounter and decoder 46 is to determine how many samples will be taken ata given rate in a minor cycle. If X samples are to be taken, the number63--)( is stored, and the decoder portion simply determines when Xsamples have been taken by detecting when a count of 63 has beenreached. Until then the detector output DLY is false, i.e. equal to 0.Thus, the transfer delay counter must be loaded from memory once foreach rate contained in each minor frame. The three bits in the presentindex register along with the signal S,,, determines the location fromwhich the transfer delay counter will be loaded. Thus the present indexregister will specify a location from 000 to 007 and the signal S willeffectively add 8 to change the address to one from 010 to 017.

The frame counter register 43 is incremented at the end of every minorframe. To accomplish that, the control word stored in the addressregister 42 includes a flag bit (CT) which is used to increment theframe count register, as noted hereinbefore. Accordingly, the flag bitin every control word in memory pointing to the address of a sample atthe rate included last in a minor frame is set equal to l, and in allother control words, equal to 0.

Once all of the samples programmed at a given rate in a minor frame havebeen sampled, there must be some way of returning to the control wordwhich points to the memory location containing the address of firstsample to be taken again during the next minor frame. A frame returndecoder 47 accomplishes that by comparing the number in the frame countregister with the contents of the present index register which not onlypoints to the location in memory from which the control address registeris to be loaded next but also is associated with the rate of the groupto be sampled next. For example, since the samples at a given rate R/2'repeat themselves every 2" minor frames, and since the present indexregister is loaded with the number n for the current rate groups ofsamples, when the frame count register reaches the minor frame count of2" for that rate group, the frame return decoder 47 transmits a signalFRF. The control address register will then be loaded from the samememory location as it was during the first minor frame, i.e., from aninitial condition location in the block 020 to 027. Which of the eightlocations depends upon the content of the present index register whichwill be an octal digit from to 7 for the respective memory locationsfrom 020 to 027. An advantage of this arrangement is that theprogrammable access telemetry system will automatically recycle to aninitial condition so that any transient which may cause an errorsequencing through any given rate groups will not be carried forwardindefinitely.

The control word in the address register 42 is incremented after eachsample and then stored in a scratch pad memory in order that it point tothe memory location of the data identification word (DATAID/LP) for thesensor or digital data source to be sampled in the same rate group.Incrementing is automatic unless the data identification word has a bit1 in a flag position (LP) as noted hereinbefore. Therefore, is Ll l fora given data source, the system will return to the same memory locationin the block from 030 to 377 each time the corresponding control word iscalled out for the particular rate group until the frame return signalFRF occurs. That allows successive multiple sampling from a singlesource. Each time the memory 16 is addressed, a memory addressing unit16b is controlled by the address from the appropriate register bysequence control signals S S S and S either directly or conditionallythrough gates.

It should be clearly understood that each channel of each minor framerequires one 7-step cycle of the waveforms shown in FIG. 2 and generatedas described with reference to FIG. 3. Therefore an understanding ofthat cycle will aid in understanding the system of FIG. 4. To facilitatethat, the flow chart shown in FIG. 6 will be described in conjunctionwith a further description of FIG. 4.

As noted hereinbefore a START command signal initiates the first cyclefor the first minor frame. The cycle repeats automatically until an EXITcommand is received. The START command resets the new index register 45,resets the frame count register 43 and sets the transfer delay counterand decoder to the count of 63. It also sets the flip-flop 33 (FIG. 3).The first step then transfers the contents of the new index register 45(which is not octal 0) to the present index register 44 to point to thememory location for the control word to be used in addressing the firstrate group of channels in sequence. The control for that is through agate 60 enabled by the sequencing signal S A Signal DLY from thetransfer delay counter and decoder 46 will be true at this time (becauseit has just been set to 63 to make it possible.

In step 2, the first control word is transferred from the memorylocation specified by the present index register (which is now octal 0)plus 16 (which is equal to 020). The frame return flag FRF from thedecoder 47 (now equal to I because both registers 43 and 44 are at 0)signifies that an initial condition location is to be used and not amemory scratch pad location. Gate 61 provides timing control during thisoperation and gate 62 provides the plus 16" control. In step 3, thetransfer delay counter and new index register are loaded from a memorylocation 010 specified by the number in the present index register(which is still octal 0) and the timing signal That is done by applyingthe signal S, to the memory addressing unit to combine a binary l withthe three binary 0s in the present index register to obtain the octalcode 010. The new index is a filed of three bits of a nine-bit word readfrom the memory location 010. The balance of the nine-bit word go to thedelay counter. A gate 63 provides timing control for this operation.That completes preparation for the first cycle with initial conditionstaken from memory locations 010 and 020. For Subsequent cycles whichstart a new rate group, operation of the sequence control unit is muchthe same as will be presently understood.

In step 4, the selection address register 41 is loaded from memory withthe address of the sensor or data source to be sampled as specified bythe control word in the register 42. To accomplish that, the timingsignal S. is applied to that register and the memory addressing unit.

The first sample is taken during step 5. Preparations are also madeduring step 5 for sampling the next channel by incrementing the transferdelay counter if the count of 63 has not been reached, i.e. if DLY-0,and by incrementing the control address register 42 to point to the nextmemory location in sequence containing the address of the sensor ordigital data source to be sampled next, but only if the flag LP of thedata identification code (DATAlD/LP) in the address register for thecurrent channel is zero. Thus, as noted hereinbefore, by programming aflag LB=I in a data identification code, the system can be caused tosample the same channel repeatedly until a frame return signal FRFoccurs. This allows multiple sampling from a single memory location asshown in the format of FIG. 5, thus conserving memory locations used forthe format. A timing signal S, applied to gates 64 and 63 will respondto the signal S, to control these operations while the signal S,controls the sampling process directly, as described hereinbefore withreference to FIG. 1. Thus, if LP is 0, the control word in the register42 is incremented to fetch from memory the next data identification codeof the first rate group, and if DL Y=O the counter 46 is incremented tokeep track of the number of channels sampled in sequence.

As long as DLY remains equal to zero, no operation will take place inthe sixth and seventh steps of the current sequence control cycle, andno operation will take place in the first three steps of the next cycleeither. In the fourth step, the selection address register 41 is loadedfrom the memory location specified by the contents (control word) of theregister 42. The fifth step is then executed as before, and the processis repeated until the programmed number of samples at the first rate Rhave been taken in sequence, at which time the signal DLY becomes true(DL Y=l In the sixth step the control word (CI'LADR/CT) is stored in thescratch pad memory location 000 associated with the first rate group R,as specified by the present index register which is still at O. Theframe count register 43 is not incremented at this time, nor duringsubsequent rate group cycles, until the last, because the control wordsfor the first rate group and the subsequent rate groups prior to thelast rate group are not provided with a flag CT=1 Referring to FIG. 5,frame count register would be incremented only when the control word forthe last rate group (rate R/64) is loaded into the register 42.Initially that control word has the address for the memory location ofthe data identification code for channel 40, and the flag bit CT.Thereafter, that control word is incremented in step 5 and stored in thescratch pad memory location specified by the present index registerduring step 6. The step signal S provides control for these operationsthrough gates 66, 67 and 68. The gate 68 is enabled only when DLYistrue, i.e. not equal to 0, which is when the desired number of sampleshave been processed out of the rate group in progress. Accordingly, thatoutput controls the operation of storing CTLADR/CT in the scratch padmemory location specified by the present index register.

Each subsequent rate group is processed in the same manner. During step1, the contents of the new index register (loaded during step 3 of thefirst cycle for the last rate group) are transferred to the presentindex register to be used to load the control word for the ensuing rategroup in the register 42 during step 2, and the load the delay counterand new index register during step 3. The latter is loaded with theoctal number of the next rate group. Thus during the first rate group,the new index register is stored with the octal code 3 for the next rategroup RIB. In the exemplary format of FIG. 5, there are 32 channels tobe sampled at the same rate Rl8. That is accomplished by programming acount of four (specifically 63-4) to be loaded into the delay counter.In that manner, the next four channels 230, 220, 2l0 and 200 are sampledin sequence during the first minor frames.

During subsequent minor frames, successive subgroups of 4 are sampleduntil eight minor frames have been completed. That is detected by theframe return decoder, which, in response to the octal 3 code in thepresent index register, causes binary 's in the three least significantbit positions of the frame count register to be detected. The framecount register is, of course, incremented by only the programmed flag CTin the control word of the last rate group R164.

It should be noted that for the rate group R18 of 32 channels, the dataidentification codes 230, 220 231, 221 239, 229 207 are stored insuccessive memory locations in the block from 030 to 377 in order forone control word (CT LADR/CT) to be used for all 32 channels. It shouldalso be noted that although all possible rate groups need not beincluded in a minor frame, any one rate group can be included only once.Therefore, all channels to be sampled at the same rate must be groupedtogether using subgroups as just illustrated for 32 channels at the rateR18.

Storing the control word from the register 42 in a memory location ofthe scratch pad memory specified by the rate group code in the presentindex register in step 6 will allow the next minor frame to proceed withthe next channel of the same rate group in sequence during the nextminor frame. No operation takes place during step 7. The period for thatstep is provided in the sequence control unit cycle to allow for thelast bit of a seven bit number to be serially transferred into the realtime data buffer 18 or the data processing and monitoring unit,whichever is specified by operation-code bits read into the register 41as part of the data identification code. The operation-code bits areapplied to the data buffer 18 and the monitoring unit l9 to controloperation of those units for the data then being sampled. It should benoted that if additional time is required, such as for data processing,before another sample is taken in sequence, the sequence control unitcycle can be extended to include additional idle steps following step 7before recycling to step I.

If an EXIT command has not been received by step 7, Le. EXJT=0 beforestep 1 of any cycle, the 7-step cycle will be repeated starting withstep 1; otherwise, the operation of the sequence control unit isterminated until another START command is received at which time thesystem will automatically go to a fixed program sequence to load thememory from the GP computer.

The frame return decoder first decodes the rate group number in thepresent index (P, P P register as 0, l ...7 for the rate groups R, R/2R, 128 to generate signals X,,, X ...X,, respectively, and then decodesthe frame count register bits C,, to C to generate the FRF signal asfollows:

In that manner, the operation specified in steps 2 will use eitherinitial condition" memory locations 020 to 027 for control words, or thescratch pad memory locations 000 to 007 according to the following logicequations:

INITIAL coNDlTlONlS DLY FRF) P, P, P,, (S DLY FRF) s, P, P, P,

Following that, in step 3, the delay counter and present index registerare loaded from the respective memory locations specified by the controllogic (S, DLY FRF) S, P, P P Thus, finally on step 6, the contents ofthe control address register is stored in scratch pad memory at alocaiion specified by the present index register and control logic (SDLY FRF) 3;, P, P P The next rate group is then introduced and the delaycounter 46 is loaded with an appropriate number which will cause DLY tobe equal to i when it has been incremented the required number of times.All subsequent rate groups are similarly introduced until the last rategroup is introduced. The control word for that last rate group includesa bit CT which causes the frame count register 43 to be incremented. Asa transition is made from one rate group to another during each minorframe, the scratch pad location is used to store the control word forthe next sample of the one rate group.

Although particular embodiments of the invention have been described andillustrated herein, it is recognized that modifications and variationsmay readily occur to those skilled in the art. For example, to permitindirect addressing of data source identification words in the memorylocations 030 to 377, the LP flag may be expanded to include a secondbinary digit. The binary code 00 would permit the control word CT- LADRin the register 42 to be incremented as before, and the binary code 01would inhibit the control word from being incremented. The code 11 wouldthen be used to both inhibit the control word from being incremented andto cause the content of the selection address register to be transferredto the control address register, and the code ll would also inhibitselection of a data source, all during step 5. The stored word DATAlD/LPhaving Lkll is then not a data source identification but simply a wordhaving a control word filed (CI'LADR) to be substituted for the presenton in the register 42. Thus, at the expense of just one sequencing unitcycle, the format can be programmed to jump from one memory location toany other memory location for the data source identification word of thenext sample. This indirect addressing possibility can be used tofacilitate altering an existing format in memory without rewriting orrearranging the entire format.

Another example of a useful modification is an expansion of the rategroup identification code to four or more bits in order to have morethan seven rate groups, each with one associated memory location fromeach of three blocks of memory as before. A variant would be to useadditional bits to specify second groups of the same rates. Forinstance, assuming a four bit code, the three least significant bits canbe used for seven distinct rate groups as before with a bit zero in thefourth bit position, and for seven alternate rate groups of the samerates as the seven distinct rate groups with a bit one in the fourth bitposition. In that manner, a given rate group can be included in thefonnat twice, each time for a different set of sensors and data sources.

Still other modifications and variations will occur to those skilled inthe art. Consequently, it is intended that the claims be interpreted tocover such modifications and variations.

What is claimed is:

1. A programmable telemetry system comprising a memory unit having aplurality of randomly accessible memory locations for storing digitalsignals representing control words for sampling predetermined sources ofdata at different rates in a desired format, digital signalsrepresenting identification codes of said data sources, and digitalsignals representing the number of data sources to be sampled insequence at a given rate,

a first register coupled to said memory unit for receiving dataidentification code words in rate groups from predetermined memorylocations, all groups except one consisting of a plurality of datasources to be sampled at a desired rate, R12" where n is a positiveinteger, relative to said one group which is to be sampled cyclically ata rate R, each group being stored in a unique block of memory locations,

a second register coupled to said memory unit for receiving controlwords in a predetermined order, each control word specifying the memorylocation of the first data identification code word of a unique rategroup,

a delay counter coupled to said memory unit for receiving digitalsignals representing a delay word in the form of a number specifying thenumber of data sources of a given rate group to be sampled in sequenceduring one minor frame cycle, where a minor frame is defined as theinterval between samples of a given data source occurring once in thehighest rate group, and for counting the number of successive samplestaken from a given rate group, and

sequence control means for loading control words into said secondregister one at a time from a predetennined block of memory locations,for loading delay words into said counter, one delay word for eachcontrol word from a predetermined group of memory locations, for loadingdata identification control words into said first register from memorylocations specified by the control word in said second register, eachtime incrementing both said control word in said second register andsaid delay word in said delay counter, for storing each incrementedcontrol word within another predetermined block at a memory locationuniquely associated with the rate group controlled by the incrementedcontrol word being stored when the number of samples specified by saiddelay word have been taken, and for loading a given control word intosaid second register from either said predetermined block of memorylocations reserved for unincremented control words or from said blockreserved for for incremented control words depending upon whether all ofthe samples from the rate groups controlled have just been completedduring the previous minor frame cycle.

2. The combination defined by claim 1 wherein each unincremented controlword loaded into said second register includes a flag indicating whetheror not the rate group controlled thereby is the last rate group of aminor frame cycle, and said flag is stored with each incremented controlword in said memory location uniquely associated with the rate group,each rate group R12 is identified by the number 11 representing theexponent of 2 by which the highest rate is divided to determine itsgroup rate, and said sequence control unit includes a third register,

means for loading into said third register said number n associated withthe rate group being controlled by the control word in said secondregister,

frame counting means for counting in binary form the number of timessaid flag, loaded into said second register with a control word,indicates that the rate group controlled thereby is the last of a minorframe,

means responsive to said number n in said third register for generatinga frame return flag when the n least significant binary digits are eachequal to zero, and

means responsive to said frame return flag for causing the control wordfor a given group to be loaded from a memory location reserved for anunincremented control word for the group of the group rate associatedwith the number n, and for causing an unincremented control word for thegroup of the highest group rate R to always be loaded from a memorylocation reserved for an unincremented control word.

3. The combination defined by claim 2 wherein which of saidpredetermined group of memory locations for unincremented control wordsis, in each instance, selected from a group of 11 memory locations,where the addresses for the cations in the two groups is comprised inthe least significant parts of the numbers 0 to n, such that memorylocations 0 to n are reserved for the respective rate groups R, R/Z,,R/2".

4. The combination defined by claim 3 wherein each delay word for agiven rate group is read from a memory location in a unique block of nmemory locations, each location of said block is identified by thenumber n in the leat significant portion of its address, and the numbern identifying the rate group to be sampled next is read from the samememory location as said delay word for the current rate group to besampled, and at the same time, including a fourth register into whichsaid number n is read while said delay word is being entered into saiddelay counter, and

means for transferring the content of said fourth register to said thirdregister when said delay counter has counted a number of samplesspecified by said delay word.

5. The combination defined by claim 4 including a source of system clockpulses,

a cyclic timing means connected to said source of clock pulses andresponsive thereto for generating a cyclical sequence of step controlsignals, and

wherein said sequence control means responds to said step controlsignals to transfer the content of said fourth register to said thirdregister during the first step, to load said second register from amemory location specified by the content of said third register and saidframe return flag during the second step, to load said delay counter andsaid fourth register from a memory location specified by said thirdregister during the third step, to load said first register from amemory location specified by said second register during the fourthstep, to increment said delay counter if the delay count is notcomplete, to increment said second register and select the data sourcespecified by said first register during said fifth step, and, if, duringthe sixth step the number of samples specified by said delay count hasbeen taken, to increment said frame counting means if said flag loadedinto said second register with a control word during the second stepindicates that the rate group controlled thereby is the last of a minorframe, and to store the incremented control word in a memory locationspecified by said third register; otherwise, if the number of sampleshas not been taken, to recycle to the fourth step from the fifth step.

6. The combination defined by claim 5 wherein said sequence controlmeans recycles to the fourth step from the fifth step through idlesixth, first, second and third steps in order to allow the same amountof time for processing each sample.

7. The combination defined by claim 6 wherein there is at least oneadditional idle step following each sixth step to allow sufficient timefor processing of sampled data.

8. The combination defined by claim 7 wherein each data identificationcode includes a repeat flag code which, when set to a predeterminedvalue, indicates that the sample specified be taken repeatedly duringsuccessive sequencing cycles until the number of samples specified bysaid delay word for a given rate group has been taken, and wherein thestep of incrementing said second register is conditioned on said repeatflag code of a given data identification code not being set to saidpredetermined value.

9. The combination defined by claim I wherein each data identificationcode word includes a flag code which, when at a predetermined value,indicates the same data identification code word is to be used again,and said sequence control means includes means for inhibiting saidcontrol word in said second register from being incremented, whereby thesame data identification code word is used for successive samples untilthe number of samples specified by said delay word has been taken.

10. A programmable telemetry system comprising a memory unit having aplurality of randomly accessible memory locations for storing digitalsignals representing control words for sampling predetermined sources ofdata at different rates in a desired format, digital signalsrepresenting identification codes of said data sources, and digitalsignals representing the number of data sources to be sampled insequence at a given rate,

a first register coupled to said memory unit for receiving dataidentification code words in rate groups from predetermined memorylocations, all groups except one consisting of plurality of data sourcesto be sampled at a desired rate, R/Z" where n is a positive integer,relative to said one group which is to be sampled cyclically at a rateR, each group being stored in a unique block of memory locations,

a second register coupled to said memory unit for receiving controlwords in a predetermined order, each control word specifying the memorylocation of the first data identification code word of a unique rategroup, and

sequence control means for loading a control words into said secondregister from a predetermined block of memory locations, loading dataidentification control words into said first register from memorylocations specified by the control word in said second register, eachtime incrementing said control word in said second register, storingeach incremented control word within another predetermined block at amemory location uniquely associated with the rate group controlled bythe incremented control word being stored and loading a given controlword into said second register from either said predetermined block ofmemory locations reserved for unincremented control words or from saidblock reserved for for incremented control words depending upon whetherall of the samples from the rate groups have just been completed duringthe previous minor frame cycle, where a minor frame is defined as theinterval between samples of a given data source occurring once in thehighest rate group.

i l. The combination defined in claim wherein each unincrernentedcontrol word loaded into said second register includes a flag indicatingwhether or not the rate group controlled thereby is the last rate groupof a minor frame cycle, and said flag is stored with each incrementedcontrol word in said memory location uniquely associated with the rategroup, each rate group R/2" is identified by the number n representingthe exponent of 2 by which the highest rate is divided to determine itsgroup rate, and said sequence control unit includes a third register,

means for loading into said third register said number n associated withthe rate group being controlled by the control word in said secondregister,

frame counting means for counting in binary form the number of timessaid flag, loaded into said second register with a control word,indicates that the rate group controlled thereby is the last of a minorframe,

means responsive to said number n in said third register for generatinga frame return flag when the n least significant binary digits are eachequal to zero, and

means responsive to said frame return flag for causing the control wordfor a given group to be loaded from a memory location reserved for anunicremented control word for the group of the group rate associatedwith the number n, and for causing an unincremented control word for thegroup of the highest group rate R to always be loaded from a memorylocation reserved for an unincremented control word.

12. The combination defined in claim 11 wherein which of saidpredetermined group of memory locations for unincremented control wordsis, in each instance, selected from a group of n memory locations, wherethe addresses for the locations in the two groups is comprised in theleast significant parts of the numbers 0 to n, such that memorylocations 0 to n are reserved for the respective rate groups R, R/2,R/Z".

1. A programmable telemetry system comprising a memory unit having aplurality of randomly accessible memory locations for storing digitalsignals representing control words for sampling predetermined sources ofdata at different rates in a desired format, digital signalsrepresenting identification codes of said data sources, and digitalsignals representing the number of data sources to be sampled insequence at a given rate, a first register coupled to said memory unitfor receiving data identification code words in rate groups frompredetermined memory locations, all groups except one consisting of aplurality of data sources to be sampled at a desired rate, R/2n where nis a positive integer, relative to said one group which is to be sampledcyclically at a rate R, each group being stored in a unique block ofmemory locations, a second register coupled to said memory unit forreceiving control words in a predetermined order, each control wordspecifying the memory location of the first data identification codeword of a unique rate group, a delay counter coupled to said memory unitfor receiving digital signals representing a delay word in the form of anumber specifying the number of data sources of a given rate group to besampled in sequence during one minor frame cycle, where a minor frame isdefined as the interval between samples of a given data source occurringonce in the highest rate group, and for counting the number ofsuccessive samples taken from a given rate group, and sequence controlmeans for loading control words into said second register one at a timefrom a predetermined block of memory locations, for loading delay wordsinto said counter, one delay word for each control word from apredetermined group of memory locations, for loading data identificationcontrol words into said first register from memory locations specifiedby the control word in said second register, each time incrementing bothsaid control word in said second register and said delay word in saiddelay counter, for storing each incremented control word within anotherpredetermined block at a memory location uniquely associated with therate group controlled by the incremented control word being stored whenthe number of samples specified by said delay word have been taken, andfor loading a given control word into said second register from eithersaid predetermined block of memory locations reserved for unincrementedcontrol words or from said block reserved for for incremented controlwords depending upon whether all of the samples from the rate groupscontrolled have just been completed during the previous minor framecycle.
 2. The combination defined by claim 1 wherein each unincrementedcontrol word loaded into said second register includes a flag indicatingwhether or not the rate group controlled thereby is the last rate groupof a minor frame cycle, and said flag is stored with each incrementedcontrol word in said memory location uniquely associated with the rategroup, each rate group R/2n is identified by the number n representingthe exponent of 2 by which the highest rate is divided to determine itsgroup rate, and said sequence control unit includes a third register,means for loading into said third register said number n associated withthe rate group being controlled by the control word in said secondregister, frame counting means for counting in binary form the number oftimes said flag, loaded into said second register with a control word,indicates that the rate group controlled thereby is the last of a minorframe, means responsive to said number n in said third register forgenerating a frame return flag when the n least significant binarydigits are each equal to zero, and means responsive to said frame returnflag for causing the control word for a given group to be loaded from amemory location reserved for an unincremented control word for the groupof the group rate associated with the number n, and for causing anunincremented control word for the group of the highest group rate R toalways be loaded from a memory location reserved for an unincrementedcontrol word.
 3. The combination defined by claim 2 wherein which ofsaid predetermined group of memory locations for unincremented controlwords is, in each instance, selected from a group of n memory locations,where the addresses for the locations in the two groups is comprised inthe least significant parts of the numbers 0 to n, such that memorylocations 0 to n are reserved for the respective rate groups R, R/21, .. . ,R/2n.
 4. The combination defined by claim 3 wherein each delay wordfor a given rate group is read from a memory location in a unique blockof n memory locations, each location of said block is identified by thenumber n in the least significant portion of its address, and the numbern identifying the rate group to be sampled next is read from the samememory location as said delay word for the current rate group to besampled, and at the same time, including a fourth register into whichsaid number n is read while said delay word is being entered into saiddelay counter, and means for transferring the content of said fourthregister to said third register when said delay counter has counted anumber of samples specified by said delay word.
 5. The combinationdefined by claim 4 including a source of system clock pulses, a cyclictiming means connected to said source of clock pulses and responsivethereto for generating a cyclical sequence of step control signals, andwherein said sequence control means responds to said step controlsignals to transfer the content of said fourth register to said thirdregister during the first step, to load said second register from amemory location specified by the content of said third register and saidframe return flag during the second step, to load said delay counter andsaid fourth register from a memory location specified by said thirdregister during the third step, to load said first register from amemory location specified by said second register during the fourthstep, to increment said delay counter if the delay count is notcomplete, to increment said second register and select the data sourcespecified by said first register during said fifth step, and, if, duringthe sixth step the number of samples specified by said delay count hasbeen taken, to increment said frame counting means if said flag loadedinto said second register with a control word during the second stepindicates that the rate group controlled thereby is the last of a minorframe, and to store the incremented control word in a memory locationspecified by said third register; otherwise, if the number of sampleshas not been taken, to recycle to the fourth step from the fifth step.6. The combination defined by claim 5 wherein said sequence controlmeans recycles to the fourth step from the fifth step through idlesixth, first, second and third steps in order to allow the same amountof time for processing each sample.
 7. The combination defined by claim6 wherein there is at least one additional idle step following eachsixth step to allow sufficient time for processing of sampled data. 8.The combination defined by claim 7 wherein each data identification codeincludes a repeat flag code which, when set to a predetermined value,indicates that the sample specified be taken repeatedly duringsuccessive sequencing cycles until the number of samples specified bysaid delay word for a given rate group has been taken, and wherein thestep of incrementing said second register is conditioned on said repeatflag code of a given data identification code not being set to saidpredetermined value.
 9. The combination defined by claim 1 wherein eachdata identification code word includes a flag code which, when at apredetermined value, indicates the same data identification code word isto be used again, and said sequence control means includes means forinhibiting said control word in said second register from beingincremented, whereby the same data identification code word is used forsuccessive samples until the number of samples specified by said delayword has been taken.
 10. A programmable telemetry system comprising amemory unit having a plurality of randomly accessible memory locationsfor storing digital signals representing control words for samplingpredetermined sources of data at different rates in a desired format,digital signals representing identification codes of said data sources,and digital signals representing the number of data sources to besampled in sequence at a given rate, a first register coupled to saidmemory unit for receiving data identification code words in rate groupsfrom predetermined memory locations, all groups except one consisting ofplurality of data sources to be sampled at a desired rate, R/2n where nis a positive integer, relative to said one group which is to be sampledcyclically at a rate R, each group being stored in a unique block ofmemory locations, a second register coupled to said memory unit forreceiving control words in a predetermined order, each control wordspecifying the memory location of the first data identification codeword of a unique rate group, and sequence control means for loading acontrol words into said second register from a predetermined block ofmemory locations, loading data identification control words into saidfirst register from memory locations specified by the control word insaid second register, each time incrementing said control word in saidsecond register, storing each incremented control word within anotherpredetermined block at a memory location uniquely associated with therate group controlled by the incremented control word being stored andloading a given control word into said second register from either saidpredetermined block of memory locations reserved for unincrementedcontrol words or from said block reserved for for incremented controlwords depending upon whether all of the samples from the rate groupshave just been completed during the previous minor frame cycle, where aminor frame is defined as the interval between samples of a given datasource occurring once in the highest rate group.
 11. The combinationdefined in claim 10 wherein each unincremented control word loaded intosaid second register includes a flag indicating whether or not the rategroup controlled thereby is the last rate group of a minor frame cycle,and said flag is stored with each incremented control word in saidmemory location uniquely associated with the rate group, each rate groupR/2n is identified by the number n representing the exponent of 2 bywhich the highest rate is divided to determine its group rate, and saidsequence control unit includes a third register, means for loading intosaid third register said number n associated with the rate group beingcontrolled by the control word in said second register, frame countingmeans for counting in binary form the number of times said flag, loadedinto said second register with a control word, indicates that the rategroup controlled thereby is the last of a minor frame, means responsiveto said number n in said third register for generating a frame returnflag when the n least significant binary digits are each equal to zero,and means responsive to said frame return flag for causing the controlword for a given group to be loaded from a memory location reserved foran unicremented control word for the group of the group rate associatedwith the number n, and for causing an unincremented control word for thegroup of the highest group rate R to always be loaded from a memorylocation reserved for an unincremented control word.
 12. The combinationdefined in claim 11 wherein which of said predetermined group of memorylocations for unincremented control words is, in each instance, selectedfrom a group of n memory locations, where the addresses for thelocations in the two groups is comprised in the least significant partsof the numbers 0 to n, such that memory locations 0 to n are reservedfor the respective rate groups R, R/21, . . . ,R/2n.